Mark Klare

Abstract

The design, simulation, fabrication and testing of .75um PMOS transistors is studied in this work. The process uses Direct Write Electron Beam Lithography for all lithography steps. The process is matched for the tool set at The Rochester Institute of Technology and their accompanying process hurdles. As of the beginning of this work, there had been no work done on obtaining a sub-micron transistor due to limitations in the optical lithography tools available at The Rochester Institute of Technology. A process flow that is robust, but as efficient as possible is used to obtain a working sub-micron PMOS transistor.

Library of Congress Subject Headings

Power transistors--Design; Metal oxide semiconductors--Design

Publication Date

5-16-1996

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Fuller, Lynn

Advisor/Committee Member

Turkman, Renan

Advisor/Committee Member

Ramanan, S.

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.99.M44 K527 1996

Campus

RIT – Main Campus

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