Abstract

In mixed signal systems, the Phase Locked Loop (PLL) forms an integral part of the clock distribution scheme. The PLL is used to generate a local clock frequency, which is much higher than the external clock. The performance of a PLL is greatly influenced by the Voltage Controlled Oscillator (VCO). Any nonlinearity introduced by the VCO affects the synchronization between operation of on-chip circuitry and the external components. The jitter or phase noise of a VCO is the most important non-ideality. Phase noise or jitter becomes critical as system frequency increases. The source of timing error maybe due to various noise sources, with power supply noise and that due to substrate coupling being the major contributors. The thesis presented here deals with the effect of these two noise sources on the time period of the VCO. The peak cycle jitter and cycle-to- cycle jitter due to noise is estimated by developing a relation between the noise source and the deviation in the output voltage in terms of the circuit parameters. First crossing theory approximation has been used to convert the voltage error to timing error. The theory has been extended to analyze the timing error when the two noise sources are present together. Good agreement has been shown between the theoretical prediction and the simulated result. The analysis can be extended to any number of stages for any operating frequency as will be demonstrated in the subsequent chapters.

Library of Congress Subject Headings

Oscillators--Design and construction; Electronic circuits--Noise; Electronic noise; Phase-locked loops

Publication Date

5-1-2002

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Amuso, V.

Advisor/Committee Member

Madhu, S.

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7872.O7 P378 2002

Campus

RIT – Main Campus

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