Garrett Smith

Abstract

Side-channel attacks refer to a particular form of cryptanalysis in which sensitive data is revealed through information extracted from the physical implementation of a cryptosystem. An unprotected device may leak details related to operations performed on secret information through unintended inputs and outputs known as side-channels. Examples of side-channel information include power consumption, operation timing, or any other intelligence-bearing signal. Unlike traditional cryptanalytic methods, such as linear and differential cryptanalysis, side-channel attacks may be used to break cryptographic systems with no known weaknesses in the algorithm's mathematical structure. Many of these attacks may also be performed using relatively cheap and easily obtained measurement equipment, making them a significant concern for both the algorithm's design and implementation. The focus of this thesis was the implementation of a methodology for performing power analysis attacks, a type of side-channel attack in which secret information is revealed through the instantaneous power consumption of a circuit. Specifically, an attack framework was developed and applied to both protected and unprotected hardware models of the SHA-3 finalist Grøstl using gate-level circuit simulation. The results indicate that Grøstl, due to its similarities to the AES block cipher, is vulnerable to the same attacks, but also benefits from a great deal of existing research devoted to the development of effective countermeasures for AES-based devices.

Library of Congress Subject Headings

Hashing (Computer science)--Testing; Data encryption (Computer science); Cryptography--Research; Computer crimes--Prevention

Publication Date

8-1-2012

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Łukowiak, Marcin

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.H36 S64 2012

Campus

RIT – Main Campus

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