Abstract

Cryptographic operations are used throughout computing systems to protect data confidentiality and integrity. Although software implementations provide flexibility, dedicated hardware can offer more predictable execution time and reduce the processing burden placed on a general-purpose processor. This thesis presents the design and verification of a Reconfigurable Cryptographic Hardware Accelerator (RCHA) that integrates AES-128, ChaCha20, SHA-256, and BLAKE2s within a single Verilog/SystemVerilog design. A top-level interface shared by the four cores manages algorithm selection, inputs, outputs, status, protocol errors, cycle measurement, and known-answer self-tests. Verification combined primitive-level tests, integrated UVM regressions, randomized stimulus, directed coverage tests, and OpenSSL-based C++ reference models connected through DPI-C. The final integrated regression produced 401,559 passing scoreboard comparisons with no failures, reached 100.00% functional coverage in both RTL and post-synthesis runs, and reported 97.67% RTL code coverage with separate block, expression, toggle, and FSM metrics. Synthesis using a TSMC 180 nm standard-cell library produced a post-scan mapped cell area of approximately 2.418 square millimeters. The complete accelerator met the 10.000 ns clock constraint, equivalent to the 100 MHz target, with 0.827 ns of positive slack. The averaged top-level power estimate was 42.0 mW. These results show that the completed accelerator supports all four primitives through one verified interface while exposing its area, timing, benchmark-cycle, and power tradeoffs.

Publication Date

8-2026

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering

College

Kate Gleason College of Engineering

Advisor

Mark Indovina

Advisor/Committee Member

Carlos Barrios

Advisor/Committee Member

Dorin Patru

Campus

RIT – Main Campus

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