Abstract
Traditional Von-Neumann computing architectures suffer from a fundamental limitation known as the memory wall, where performance is constrained by the cost of data movement between memory and processing units rather than by computational capability. This limitation is particularly pronounced in data-intensive workloads such as machine learning (ML) and hyperdimensional computing (HDC), where matrix-vector operations dominate execution and are often memory-bound. Processing-in-Memory (PIM) architectures have emerged as a promising approach to mitigate this bottleneck by enabling computation to occur within or near memory, thereby reducing data movement overhead. However, due to these processors' specialized nature and the limited integration of general-purpose control logic in existing PIM implementations, they often lack the capability to efficiently handle matrix sparsity, limiting their ability to fully exploit the redundancy present in modern workloads. This work proposes a reconfigurable hardware architecture for efficient matrix-vector multiplication (MVM) within a PIM framework, designed to natively support both dense and structured sparse operations using N:M sparsity, including 1:2, 2:4, and 4:8 configurations. The architecture integrates a sorting-based selection mechanism, flexible routing network, and parallel compute units to enable dynamic trade-offs between computational workload and execution latency without requiring precomputed compressed data formats. Through synthesis and evaluation, the architecture demonstrates improved computational efficiency and reduced data movement, while maintaining low hardware overhead and preserving application-level accuracy. These results highlight the effectiveness of integrating structured sparsity directly into a PIM-compatible datapath for accelerating modern data-intensive workloads.
Publication Date
5-2026
Document Type
Thesis
Student Type
Graduate
Degree Name
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering
College
Kate Gleason College of Engineering
Advisor
Sathwika Bavikadi
Advisor/Committee Member
Cory Merkel
Advisor/Committee Member
Marcin Lukowiak
Recommended Citation
Avila, Timothy, "A Reconfigurable Architecture for Dense and Sparse Matrix Multiplication in Processing-in-Memory" (2026). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/12637
Campus
RIT – Main Campus
