Abstract

In a computer system, a hierarchical memory aims to give processing cores the illusion that they have access to the largest capacity memory, i.e., the disk, at the shortest access time, i.e., that of the memory level closest to them - the one-, two-, or three- levels of cache. Therefore, an efficient operation of the cache is key to lowering the average memory access time. Toward this end, lowering the miss rate, which is the principal metric of cache performance, is the goal of any cache implementation. Traditional caches are automatic and reactive. Several prior iterations of this work have introduced and explored a special kind of programmable and (implicitly) prescriptive cache: a lease cache. In this prior work lease values are static, i.e., would not change at run-time, and in the absence of expired leases, the target cache line of a forced eviction (victim) is selected pseudo-randomly. In this work, we introduce and present the hardware implementation and test results of two alternative eviction optimizations and dynamically (at runtime) adjusted lease values. The former two decide a eviction target by tracking and using the history of utilization of all blocks of data at word level. The latter augments static with dynamic information to adjust reference lease values. Test results show equal or lower miss rates than those with static leases, overall lower than PLRU, and in many cases close to OPT.

Library of Congress Subject Headings

Cache memory--Optimization; Memory management (Computer science); Compilers (Computer programs)

Publication Date

8-2025

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical and Microelectronic Engineering, Department of

College

Kate Gleason College of Engineering

Advisor

Dorin Patru

Advisor/Committee Member

Chen Ding

Advisor/Committee Member

Mark Indovina

Campus

RIT – Main Campus

Plan Codes

EEEE-MS

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