Abstract

As microchips become more complex, smaller, and faster, the clock skew and power consumption present significant design challenges. Asynchronous circuits offer a solution to these issues by replacing the global clock routing with handshaking circuitry. This thesis details the implementation of an asynchronous 32-bit RISC-V processor leveraging 4-phase bundled data handshaking to replace the clock used for synchronization. Key contributions include the development of a 4-stage pipelined RISC-V compliant processor architecture adapted for asynchronous operation, the design of a custom 45nm C-element cell crucial for handshaking synchronization, and analysis of its performance in terms of area, timing, and power. This research aims to provide a foundational basis for designing more complex asynchronous processors and explores the potential benefits gained from asynchronous circuits in terms of power efficiency compared to synchronous counterparts.

Library of Congress Subject Headings

RISC microprocessors--Design and construction; Asynchronous circuits--Design and construction

Publication Date

8-2025

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering

College

Kate Gleason College of Engineering

Advisor

Mark A. Indovina

Advisor/Committee Member

Dorin Patru

Advisor/Committee Member

Carlos Barrios

Campus

RIT – Main Campus

Plan Codes

EEEE-MS

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