Abstract
The rapid development and growing interest in Artificial Intelligence (AI) have resulted in a trend of models increasing in size and complexity at an accelerating rate. These larger models have demonstrated a greater ability to accomplish increasingly sophisticated tasks compared to smaller models, furthering the trend of making models larger. However, as the models continue to improve and grow larger, this has created a new challenge in deploying them into practical applications. Current models typically run inference on the same systems where they were trained. Large data centers comprising Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are well-suited for running these large models. However, many of the envisioned applications would require a significant reduction in size and power utilization to be effectively implemented. This research will investigate the potential of a new number system called Posits and its ability to optimize models through quantization. The potential will be tested by quantizing two CNN networks from 32-bit floating-point to 6-bit Posits, culminating in the design and verification of a hardware accelerator that implements both models in Posit form.
Library of Congress Subject Headings
Neural networks (Computer science)--Energy consumption; Convolutions (Mathematics); Computer vision; Sound--Classification; Optical pattern recognition
Publication Date
8-2025
Document Type
Thesis
Student Type
Graduate
Degree Name
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering
College
Kate Gleason College of Engineering
Advisor
Mark A. Indovina
Advisor/Committee Member
Dorin Patru
Advisor/Committee Member
Cory Merkel
Recommended Citation
Ng, Steven, "Design of a Posit Based 6-Bit Configurable CNN Hardware Accelerator for Audio and Image Classification" (2025). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/12292
Campus
RIT – Main Campus
Plan Codes
CMPE-MS
