Abstract

The subject of Quantum Computing is in its early stages of development, and new technologies and algorithms are constantly evolving. Even with all of this progress it is important to recognize that current quantum computers are still in their infancy and, as such, have notable issues. The ``era" that we are in currently is known as the Noisy Intermediate-Scale Quantum (NISQ) era, which is characterized by machines of small size that are prone to quantum noise, which causes computational error the longer the circuit runs. In order to make use of these quantum computers, algorithms need to be developed that both use a minimal number of qubits and minimize the time needed for them to run. Utilizing classical computing techniques as the inspiration for this work, the aim is to reduce "depth," which is analogous to the run-time of a quantum circuit. By taking advantage of the parallel computing techniques in classical arithmetic logic units (ALUs), we are able to create quantum circuits that can take advantage of their own parallelism, leading to a reduced run-time. In addition to the potential benefits to the complexity of the algorithm, decreasing run time reduces the potential for error to accrue and compound as the circuit runs. This approach was chosen because, while other approaches exist which focus on reducing the effects of noise, this one aims to increase the speed of the circuit itself, leading to designs that will still be preferable on future machines. Much like classical computing, small-scale circuit designs are used as building blocks for large-scale algorithms. Improvements made to a quantum multiplication algorithm could prove useful for different applications, such as modular multiplication in Shor's algorithm, or could play a role in the implementation of oracles for Grover's search algorithm. The designs presented in this thesis offer an efficiency improvement over existing quantum multipliers coming from three sources: the efficient use of addition on the phase domain (a quantum property), the classical hardware design of array multipliers, and the use of approximation in the phase domain.

Library of Congress Subject Headings

Quantum computing--Technological innovations; Fourier transformations; Multiplication

Publication Date

5-2024

Document Type

Thesis

Student Type

Graduate

Degree Name

Computer Engineering (MS)

Department, Program, or Center

Computer Engineering

College

Kate Gleason College of Engineering

Advisor

Sonia Lopez Alarcon

Advisor/Committee Member

Michael Zuzak

Advisor/Committee Member

Marcin Lukowiak

Campus

RIT – Main Campus

Plan Codes

CMPE-MS

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