Abstract

With the rise of outsourcing in Integrated Circuit (IC) fabrication processes, vulnerabilities in chip security have become a growing concern. These vulnerabilities can lead to attacks such as reverse-engineering, piracy, overproduction, and malicious modification of high-value intellectual property (IP) in a design. In light of this, a method called logic locking has been developed to protect chips prior to end-user shipment. Logic locking incorporates additional logic gates in a design to conceal a chip’s functionality during manufacture and test processes. However, recent developments have shown logic locking to be vulnerable to optical side-channel attacks. In this work, we explore these vulnerabilities and develop a logic locking enhancement system to prevent them. At the core of this system is a method called Adjoining Gates, which generates supplementary gates to be added in close proximity of existing gates known to leak key information. Adjoining Gates contain a set of inputs which are determined through analysis of a leaking gate that is being targeted. The goal of this technique is to close optical side-channels (i.e., information leaked from a system through optical emissions), which have been shown to leak key information in a logic locked circuit. Expanding on Adjoining Gates, we implement a design automation program capable of detecting and remediating any optical side-channels that leak logic locking secrets within a design. This way, Adjoining Gates can be implemented in a circuit of arbitrary size and effectively prevent leakage with minimal increase to overall circuit complexity. For the development of Adjoining Gates, vulnerabilities in logic locking were analyzed through extensive modification of an advanced optical side-channel attack method, called the Combined Logical and Physical (CLAP) attack. When applied to several benchmarks, we observed key leakage at an average of 10% of total gates in a circuit. This attack then served as the testing platform for the development of Adjoining Gates. Upon completion, we evaluated the efficacy of Adjoining Gates, demonstrating the complete cessation of optical side-channel leakage in an individual targeted gate. This led to the development of a design automation program capable of integrating Adjoining Gates throughout a circuit design. Through program analysis, we identified the primary overhead of Adjoining Gates as the added routing complexity caused by inputs leading to each added gate. As a result, we developed an optimization to the design program which reduces the number of inputs to each Adjoining Gate. This resulted in an average of 13-20% reduction in input overhead across benchmarks tested. Finally, through automated testing procedures we presented successful prevention of leakage in a set of 16 benchmarks of varying size, locking technique, and resolution. Experimental overhead calculations demonstrated a gate count increase of 1-8%, with a less than 1% utilization of total primary inputs per Adjoining Gate in a typical case implementation. Our tests also demonstrated decreasing overall runtime with decreased circuit sizes, leakage counts, and larger resolution sizes.

Library of Congress Subject Headings

Integrated circuits--Security measures; Cyberterrorism--Prevention; Gateways (Computer networks)--Security measures

Publication Date

4-2024

Document Type

Thesis

Student Type

Graduate

Degree Name

Computer Engineering (MS)

Department, Program, or Center

Computer Engineering

College

Kate Gleason College of Engineering

Advisor

Michael Zuzak

Advisor/Committee Member

Corey Merkel

Advisor/Committee Member

Dongfang Liu

Comments

This thesis has been embargoed. The full-text will be available on or around 5/20/2025.

Campus

RIT – Main Campus

Plan Codes

CMPE-MS

Download

Available for download on Tuesday, May 20, 2025

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