Abstract
Rising design complexity and smaller technology nodes are escalating fabrication costs, prompting design houses to outsource to untrusted external facilities, which raises trust and privacy concerns. These concerns stem from the risk of security breaches like IP piracy, reverse engineering, and hardware trojans. The critical need to protect design intellectual property prompted the development of logic locking, a combinational hardware security technique that corrupts the functionality of a design without the correct secret key. However, the effectiveness of logic locking varies substantially based on how and where it is implemented within a system, including the specific technique families selected, the modules locked, and the configuration of locking within each location. Exhaustively testing out each logic locking technique is computationally infeasible as there are combinatorially large numbers of logic locking configurations in a system. In this thesis, we propose a comprehensive design space modeling framework to generate accurate system-level models of the logic locking design space in arbitrary ICs by simulating a small, carefully selected portion of the design space. These models are then used to automatically identify satisfying locking configurations in a target system that achieves security goals with minimal power and area overhead. To evaluate this framework, we perform two case studies. First, we evaluate the optimality of modeling-produced solutions by simulating locking in a RISC-V ALU. The models produced by our algorithm had an average R^2 > 0.99 for all design objectives and identified a locking configuration within 96% of the globally optimal solution after simulating less than 3.8% of the design space. Second, we compare our model-based locking configuration to conventional module level locking approaches in a RISC-V processor. The locking configuration identified by our model-based approach required 29.5% less power overhead on average than conventional approaches and was the only method to identify a solution meeting all design objectives.
Library of Congress Subject Headings
Computer input-output equipment--Security measures--Computer simulation; Computer security; Hardware Trojans (Computers)--Prevention
Publication Date
4-2024
Document Type
Thesis
Student Type
Graduate
Degree Name
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering
College
Kate Gleason College of Engineering
Advisor
Michael Zuzak
Advisor/Committee Member
Marcin Lukowiak
Advisor/Committee Member
Mark Indovina
Recommended Citation
Lam, Long, "Low Power Logic Locking using Design Space Modeling to Achieve System-Wide Security" (2024). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/11722
Campus
RIT – Main Campus
Plan Codes
CMPE-MS
Comments
This thesis has been embargoed. The full-text will be available on or around 5/15/2025.