Abstract

The semiconductor industry has seen tremendous advancement lately and is expected to continue to grow since multiple industries like automobile, health care, meteorology, etc are developing dedicated chips with advancements in Artificial Intelligence (AI). These improvements also come with increased complexities. Engineers now require advanced ways to model the designs in addition to existing Hardware Description Languages (HDLs) such as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) and Verilog. One such way to model the designs is by using SystemC, which is a library of C++ classes and macros that can be used similar to an HDL for modeling hardware for functional verification and performance modeling of the design. This paper discusses a bit-exact hierarchical SystemC model written for a multi-core programmable Processor-In-Memory (pPIM) and explores the advantages it has over existing HDLs such as Verilog, SystemVerilog, or VHDL. The pPIM is a Look Up Table (LUT) based Processing In Memory (PIM) architecture that can perform parallel processing with ultra-lowlatency for implementing data-intensive applications like Deep Neural Networks (DNN) and Convolution Neural Networks (CNN).

Library of Congress Subject Headings

High performance processors; Modeling languages (Computer science); C++ (Computer program language)

Publication Date

5-2023

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Department of Electrical and Microelectronic Engineering (KGCOE)

Advisor

Mark A. Indovina

Advisor/Committee Member

Amlan Ganguly

Advisor/Committee Member

Dorin Patru

Campus

RIT – Main Campus

Plan Codes

EEEE-MS

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