Abstract

In this work, an empirical off-state model was developed for amorphous IGZO TFTs with the purpose of creating a compact model in conjunction with an existing on-state model. The implementation of the compact model was done in Verilog-A to assess the impact of parasitc elements such as source/drain series resistance, and source/drain-to-gate overlap capacitances in a 2T1C pixel circuit. A novel region of operation was presented defined as a bridge between the subthreshold and the on-state regions. Two approaches were followed to solve for the fitting parameters inside this bridge region; an analytical and an empirical approach.

The analytical solution provided the insight that there is a point where the derivatives of the on-state and the bridge region are equal. However, this solution showed non-physical behavior at some V_DS bias. Therefore, an empirical approach was followed where experimental data was used to find the V_DS dependence and eliminate the non-physical behavior. Ultimately, the compact model provided a remarkable R^2 in relation to experimental data and allowed for convergence during circuit simulation.

The parasitic element assessment was carried out and two different phenomenon were described as they relate to these elements. Charge sharing and rise and fall time were the characteristics that were present with the introduction of parasitic elements. A capacitance ratio of C_ST/C_ov =10.6pF/265.07fF≈40 was used to diminish the former. However, the large capacitances associated in the input of the driver transistor caused the falling transient to be unable to provide full voltage swing. Therefore, proper circuit functionality was not achieved based on the presented design rules. Further work is being done to diminish overlap capacitances such as self-aligned devices.

Library of Congress Subject Headings

Electronic circuit design; Thin film transistors--Design and construction; Thin film transistors--Mathematical models

Publication Date

8-2020

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Karl D. Hirschman

Advisor/Committee Member

James Moon

Advisor/Committee Member

Mark Indovina

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

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