This project involved the performance comparison of the standard RIT N-well CMOS and a proposed BiCMOS processes. Device parameters were extracted from TMA SUPREM-3 simulations and used to create NPN, PMOS, and NMOS model cards for ~ccusim simulations. Two inverter circuits, one in CMOS and one in BiCMOS were designed to drive a 5OpF load. The BiCMOS circuit was determined to be four times faster, less temperature dependent, and considerably smaller than its CMOS counterpart. These results lead to a final conclusion favoring the development and use of BiCMOS here at RIT.
"BiCMOS vs CMOS at RIT,"
Journal of the Microelectronic Engineering Conference: Vol. 5:
1, Article 19.
Available at: https://repository.rit.edu/ritamec/vol5/iss1/19