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As devices continue to shrink following the trend of Moore's law, and non-planar devices such as Fin- FETs and 3D nanostructures become more common, ultra-shallow (sub-50 nm) junctions become more desirable. Semiconductor devices are traditionally doped using a combination of ion implantation or spin-on dopant and thermal diffusion techniques; however, these have limitations such as crystalline damage, use of hazardous chemicals, or glassy skin formation. Monolayer doping (MLD) provides a non-destructive and less hazardous method for doping the silicon surface. MLD creates a self-assembled monolayer of a dopant-containing compound followed by a rapid thermal anneal to form ultra-shallow junctions with high surface concentrations. Using the dopant-containing com- pound diethyl vinylphosphonate (DVP), MLD is used to dope the source and drain of MOSFETs. A fabrication process for these devices is designed to ensure that the source and drain are not too far away from the gate, the thermal budget is limited after the MLD process (no processing >700 C), and to minimize the possibility of junction spiking. The MLD process chamber is also redesigned to be more economical and ensure process repeatability. Electrical characterization of the devices show field effect behavior, confirming that MOSFETs have been successfully fabricated and demonstrating the ability of MLD to be patterned using SiO2.

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