One of the challenges facing the semiconductor industry as the scale of transistors shrink into nanometer sizes is the creation of ultra-shallow junctions. Furthermore, device geometry is morphing from planar to 3-dimensional structures which increases the need for conformal ultra-shallow junctions. The industry has relied on ion implantation to push the boundary of semiconductor doping, however effects such as transient enhanced diffusion caused by lattice damaged by implantation have impeded the creation of the desired ultra-shallow junctions. A new technique known as monolayer doping is one strategy to help solve both ultra-shallow junction formation as well as conformal doping. Monolayer doping relies on a self-assembled monolayer of a dopant containing compound covalently bonded to the silicon lattice which is then driven into the silicon by a rapid thermal anneal. This technique has been demonstrated at Rochester Institute of Technology (RIT) previously on the small scale of pieces of wafers. To enhance the characterization of this technique the process was scaled up to accommodate full 6 inch wafers which can then be easily run through the RIT Semiconductor & Microsystems Fabrication Laboratory (SMFL). A container and process were developed which successfully doped 6 inch wafers when compared to previously collected data. The wafers were run through a standard process in the SMFL to create devices for characterization. Monolayer doping research at RIT now has an easier and faster means of doping wafers for any future research planned.
"Large Area Monolayer Doping Development,"
Journal of the Microelectronic Engineering Conference: Vol. 23:
1, Article 6.
Available at: https://repository.rit.edu/ritamec/vol23/iss1/6