An investigation of the ASML PAS5500 5X reduction i-line stepper and RIE systems capabilities of defining sub-300nm nitride sidewall spacers to create dense 200nm silicon FinFETs on a 400nm pitch has been experimentally undertaken in the SMFL at RIT. The work presented in this project involves photoresist over-exposure through annular illumination with NA equal to 0.6, sigma inner equal to 0.535, and sigma outer equal 0.9 to narrow down the critical dimensions of the photoresist features in the 200nm range. Diluted OiR620 photoresist with PGMEA 1:1 ratio is used to obtain a thin coating of 5.5nm film thickness. A thin aluminum layer was deposited and patterned and served as a hard mask for the subsequent oxide dry etching. Ideally, a thin conformal layer of nitride is deposited through low-pressure chemical vapor deposition (LPCVD) but more DOE is required to achieve smoother surface topology before silicon fin features can be adequately patterned.
"Process Development of Sidewall Spacer Features for sub-300nm Dense Silicon FinFETs,"
Journal of the Microelectronic Engineering Conference: Vol. 23:
1, Article 26.
Available at: https://repository.rit.edu/ritamec/vol23/iss1/26