Spencer Pringle

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This work endeavored to optimize and integrate a process for depositing and patterning the gate film stack of TaN, Al2O3, Si3N4, SiO2, Si (TANOS) charge-trapping flash (CTF) memory with an existing complementary metal-oxidesemiconductor process flow. Fabricated capacitance-voltage devices with T-A-N-O thicknesses of 2500˚A, 110˚A, 75˚A, and 30˚ A respectively show characteristic charge-trapping in subsequent program/erase (P/E) cycles (likely modified Fowler-Nordheim tunneling) with a maximum possible program threshold voltage of 2.7V for 5sec 28V program and minimum erased threshold voltage of -2.5V for 5sec 15V erase, w/ total P/E threshold voltage swing 5.2V. Device wafers are currently at step 22 of 67 and will be continued in the future, eventually demonstrating hot carrier injection P/E schemes.

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