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A MEMS multi-actuated bridge switch is developed and created using the RIT sub-micron CMOS process as a way to create a high speed switch with good isolation, power consumption and low loss. The bridge was imaged using a SEM before and after the bridge release. Not much difference could be seen, prompting further investigation. There was a suspicious looking bump in the middle of the bridge that led us to believe that the TEOS sacrificial layer was buried underneath polysilicon. A cross-cut of the bridge was done where the bumps could be seen transversally. A highlight etch was done, confirming our suspicions that the mystery layer was TEOS.

During processing we realized that the mask for the sacrificial TEOS layer was the inverse polarity of what was needed. The TEOS layer width was also designed too thin, which made the etching process remove too much and making further steps overlap. Recreating this layer with a wider sacrificial TEOS and the correct polarity successfully managed to get the bridge to release. Further work would involve completing the switch and electrical testing now that the bridge release has been proven.

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