For a number of years, the hardware industry has seen a drastic rise in embedded applications. Thanks to the Internet of Things (IoT) revolution, a majority of these embedded applications are shifting towards the usage of simple hardware capable of running on batteries, while being able to handle complex data and implement complex algorithms. Translating these requirements to digital design terms, the hardware is expected to have high power efficiency, be tiny and simple enough, while being capable of meeting realtime constraints and process mathematical algorithms. Looking at some of the modern DSPs, most of them have been targeting high performance and wider applications, usually resulting in higher power consumption and complex hardware. The main motivation of this paper was to implement a simple DSP design, optimized for power efficiency, while being capable of handling simple multimedia applications. Hence, an enhanced version of TMS32010 DSP is implemented with numerous modifications to the architecture, ISA, memory addressing and pipeline structure. The major enhancements include the addition of instruction level parallelism using SIMD instructions, use of a much larger data memory to be able to accommodate a larger amount of data in multimedia applications, and expansion of the data-word to 32-bits to be able support packed SIMD data and fully utilize the 32-bit ALU. The ISA, pipeline and memory access enhancements target higher power efficiency by using a single clock across the design.

Publication Date


Document Type

Master's Project

Student Type


Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)


Mark A. Indovina

Advisor/Committee Member

Sohail A. Dianat


RIT – Main Campus