In regards to data transmission in communication systems, there is need for robust emulation of communication channels via Gaussian noise generation. Over time, larger sample sizes are desired to reach farther into the tail ends of the distribution and faster sample generation speeds are desired versus the software implementations. This paper proposes a Gaussian noise generator utilizing the Box-Muller method written in Verilog HDL targeting a 65nm ASIC process utilizing Synopsys Design Compiler. The design creates two 24-bit noise samples per clock cycle and each sample is accurate to one unit in the last place. A sample can represent up to 9.42σ, which allows for a sample size of 2 · 1020. The design generates 800 million samples/s at a clock frequency of 400MHz. After a thorough error analysis, a bit-exact model was created in MATLAB and a thorough probability and statistic analysis was executed on the generated sample sets.

Publication Date


Document Type

Master's Project

Student Type


Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)


Mark Indovina

Advisor/Committee Member

Sohail A. Dianat


RIT – Main Campus