The instruction set of a processor is embodied in the particular micro-architecture representing the processor hardware. Verifying proper operation of the instruction set for a particular processor hardware implementation requires exhaustive testing to expose unknown dependencies and other elusive design flaws. This paper presents the research and development of a flexible micro-architectural model written in SystemC for a RISC processor based upon a user defined configuration database; the RISC processor is based on an architecture assigned in course Design of Computer Systems (DCS) offered at Rochester Institute of Technology (RIT). This model will be tested by a test bench written in SystemVerilog, using randomly generated instructions, and results will be compared with various DCS student processors originally developed at the Register Transfer Level (RTL) in a Hardware Description Language (HDL) such as Verilog or VHDL. The test bench will provide stimulus such as the system clock and random instructions through a program memory attached to both the model and RTL processor. The main goal of this work is to automate verification and validation of a diverse set of processors designed in RTL by using an appropriate configuration database and comparison of all states and signals from the processor being tested and the model developed by the author. The test results will be compared and discussed.

Publication Date


Document Type

Master's Project

Student Type


Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)


Mark A Indovina

Advisor/Committee Member

Sohail A Dianat


RIT – Main Campus