Abstract

At the Rochester Institute of Technology, a freshmen laboratory project, utilizing a NOR logic array and the existing PMOS process, has been successfully incorporated into the microelectronic engineering curriculum. This paper outlines the structure of this new course. Students are introduced to digital logic and I.C. fabrication by designing a simple digital circuit and realizing it in the gate array. Completion of the circuit is accomplished by making a mask and photolithographically defining the metal layer. The circuits are then tested for functionality.

Publication Date

5-1-1987

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Lynn Fuller

Advisor/Committee Member

Ken Hsu

Advisor/Committee Member

Robert Pearson

Comments

Physical copy available from RIT's Wallace Library at TK7874 .L35 1987

Campus

RIT – Main Campus

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