The increasing heterogeneity of computing systems enables higher performance and power efficiency. However, these improvements come at the cost of increasing the overall complexity of designing such systems. These complexities include constructing implementations for various types of processors, setting up and configuring communication protocols, and efficiently scheduling the computational work. The process for developing such systems is iterative and time consuming, with no well-defined performance goal. Current performance estimation approaches use source code implementations that require experienced developers and time to produce.

We present a framework to aid in the design of heterogeneous systems and the performance tuning of applications. Our framework supports system construction: integrating custom hardware accelerators with existing cores into processors, integrating processors into cohesive systems, and mapping computations to processors to achieve overall application performance and efficient hardware usage. It also facilitates effective design space exploration using processor models (for both existing and future processors) that do not require source code implementations to estimate performance.

We evaluate our framework using a variety of applications and implement them in systems ranging from low power embedded systems-on-chip (SoC) to high performance systems consisting of commercial-off-the-shelf (COTS) components. We show how the design process is improved, reducing the number of design iterations and unnecessary source code development ultimately leading to higher performing efficient systems.

Library of Congress Subject Headings

Field programmable gate arrays--Design and construction; Graphics processing uings

Publication Date


Document Type


Student Type


Degree Name

Computing and Information Sciences (Ph.D.)


Sonia Lopez Alarcon

Advisor/Committee Member

Marcin Łukowiak

Advisor/Committee Member

Matthew Fluet


Physical copy available from RIT's Wallace Library at TK7895.G35 S52 2015


RIT – Main Campus

Plan Codes