Abstract

The Pipelined Interconnect Free (PIF) logic design methodology has the potential to eliminate several problems that are faced by the modern technology digital designers. It is very easy to model and it gives an exact idea of the circuit layout during design phase only as it uses only one type of gate and does not have any global interconnects. The thesis discusses the PIF logic circuits, their applications and performance. It discusses the full implementation of a PIF one bit full adder starting from schematic to layout stage. It discusses the issues related to the implementation of larger PIF logic circuit like a multiplier. The thesis also explains the design of an automated CAD tool which will have an interface for schematic entry of the PIF logic circuit and will generate the physical layout for the circuit in the form of a CIF file. The tool functioning is demonstrated by the implementation of a one bit PIF full adder and 2X2 multiplier.

Library of Congress Subject Headings

Interconnects (Integrated circuit technology); Logic design; Computer-aided design; Integrated circuits--Very large scale integration

Publication Date

2004

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Dorin Patru

Advisor/Committee Member

P Mukund

Advisor/Committee Member

Syed Islam

Comments

Physical copy available from RIT's Wallace Library at TK7874.53 .A82 2004

Campus

RIT – Main Campus

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