A number of SRAM-based field-programmable gate arrays (FPGAs) allow for partial reconfiguration, allowing a part of the device to be reconfigured while the rest of the device continues operating. Partial evaluation, or instance-specific design, allows a design to be optimized to a specific set of inputs. When combined with partial reconfiguration, the reconfigurable module can be reinstantiated based on the inputs to be processed and improve the performance of the design. This thesis explores the effects, particularly the performance vs flexibility tradeoff, of using partial evaluation on the color look-up tables (CLUTs) of a color-space conversion module implemented on an FPGA. This thesis examines the impact of implementing the CLUTs as distributed RAMs, distributed ROMs, and block ROMs, as well as examining the effects of initializing block RAMs.

Library of Congress Subject Headings

Image processing--Digital techniques; Field programmable gate arrays--Design and construction; Colorimetry

Publication Date


Document Type


Department, Program, or Center

Microelectronic Engineering (KGCOE)


Patru, Dorin


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TA1637 .H42 2012


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