The importance of semiconductor device fabrication has been rising steadily over many years. Integrated circuit technology and innovation depends on successful research and development (R&D). R&D establishes the direction for prevailing technology in electronics and computers. To be a leader in the semiconductor industry, a company must bring technology to the market as soon as its application is deemed feasible. Using suitable production control methods for wafer fabrication in R&D fabs ensures reduction in cycle times and planned inventories, which in turn help to more quickly, transfer the new technology to the production fabs, where products are made on a commercial scale. This helps to minimize the time to market. The complex behavior of research fabs produces varying results when conventional production control methodologies are applied. Simulation modeling allows the study of the behavior of the research fab by providing statistical reports on performance measures. The goal of this research is to investigate production control methods in semiconductor R&D fabs. A representative R&D fab is modeled, where an appropriate production load is applied to the fab by using a representative product load. Simulation models are run with different levels of production volume, lot priorities, primary and secondary dispatching strategies and due date tightness as treatment combinations in a formally designed experiment. Fab performance is evaluated based on four performance measures, which include percent on time delivery, average cycle time, standard deviation of cycle time and average work-in-process. Statistical analyses are used to determine the best performing dispatching rules for given fab operating scenarios. Results indicate that the optimal combination of dispatching rules is dependent on specific fab characteristics. However, several dispatching rules are found to be robust across performance measures. A simulation study of the Semiconductor & Microsystems Fabrication Laboratory (SMFL) at the Rochester Institute of Technology (RIT) is used to verify the results.

Library of Congress Subject Headings

Semiconductor wafers--Production control--Mathematical models; Semiconductors--Testing--Mathematical models

Publication Date


Document Type


Student Type


Degree Name

Industrial and Systems Engineering (MS)

Department, Program, or Center

Industrial and Systems Engineering (KGCOE)


Kuhl, Michael - Chair

Advisor/Committee Member

Hirschman, Karl

Advisor/Committee Member

Sudhakar, Paidy


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