Brian Dinse


NMOS and PMOS Single-crystal-silicon-on-insulator (SOI) MOSFETs have been fabricated at RIT using a Bonded and Etched-back process for substrate formation. A test chip, containing inverters, contact and sheet resistance structures, and various NMOS and PMOS transistors, was fabricated on a 2000A SOI substrate formed by a Bonded and Etched-back technique. Effective mobilities, subthreshold swings, and threshold voltages of the fabricated devices were extracted to investigate the impact of a Bonded and Etched-back process on device performance. A hole mobility of 486 cm2/V-s was obtained in PMOS SOI, comparable to state-of-the-art, and exceeding any mobility previously reported at RIT. A subthreshold swing of 11OmV/decade was observed in PMOS SOI. The NMOS devices were found to be inferior to those fabricated external to RIT using this SOI process. It was found that hole mobility increased by 14% on average and electron mobility increased by 6% on average for SOI devices compared to similar conventional devices fabricated in bulk silicon. Subthreshold swing decreased 93% on average for SOI devices compared to conventional bulk-silicon devices. SOI is identified as an attractive process, having significant performance advantages over bulk-silicon devices.

Library of Congress Subject Headings

Metal oxide semiconductor field-effect transistors--Design and construction; Silicon-on-insulator technology

Publication Date


Document Type


Department, Program, or Center

Electrical Engineering (KGCOE)


Kurinec, S.

Advisor/Committee Member

Fuller, Lynn


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.95.D56 1994


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