A 10 bit 15Mhz Analog-to-Digital converter (ADC) has been designed using a novel three step conversion technique. Successive 4bit, 3bit, and 3bit flash cycles are done for a complete conversion. Each flash cycle uses 15 comparators even though the second and third cycles require only seven comparators. The eight extra comparators are used for 4LSB digital error correction. Since, the ADC requires more than one clock cycle for a complete conversion two parallel comparator banks are used to obtain the 15Mhz conversion rate. A test chip has been designed with a 2 micron, double metal, single polysilicon, nwell CMOS technology. The size is 10.0mm2 including the pad area and 7.6mm2 without.

Library of Congress Subject Headings

Analog-to-digital convertors--Design and construction

Publication Date


Document Type


Department, Program, or Center

Electrical Engineering (KGCOE)


Fuller, Lynn

Advisor/Committee Member

Renan, Turkman

Advisor/Committee Member

Pearson, Robert


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7887.6.T48 1993


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