The development of an analog/digital mixed-mode BiCMOS process is presented. The process uses the RIT factory n-well CMOS process as its baseline process. The process is tailored to meet the requirements of an analog/digital system, while minimizing process complexity and maximizing compatibility with the established CMOS process. The process development includes determining the device requirements for the BiCMOS process, evaluating the established CMOS process, and integrating the additional process steps into the baseline process. TMA SUPREM III 1-D Process Analysis Program and RIT's processing history are used as guidelines, keeping manufacturability an important issue. An integrated test chip is developed to measure the performance of the process and to compare measured results with modelling simulations. The test chip includes test structures for each masking level, along with test circuits that are designed using CMOS, bipolar, and BiCMOS technologies, which perform analog and digital functions. The process is implemented into the RIT factory, utilizing the WIPTRACK tracking system. Each processing step is entered into the system with complete instructions. Real-time measurement data is entered into the system at each step by operators under the supervision of the process engineer. Analysis of the test structures and test circuits will demonstrate the performance of the designed process.

Library of Congress Subject Headings

Bipolar integrated circuits; Metal oxide semiconductors, Complementary

Publication Date


Document Type


Department, Program, or Center

Electrical Engineering (KGCOE)


Fuller, Lynn

Advisor/Committee Member

Turliman, Ronan

Advisor/Committee Member

Pearson, Robert


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.99.M44 H54 1992


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