Abstract

The development of a methodology to integrate design automation with the fabrication of very large scale integrated circuits is presented. A multiplier circuit is used as an example of a full custom circuit development, simulation and layout using Apollo workstations. Several other circuits, such as a 16x1 static random access memory (SRAM), a three bit counter, and a stepper motor controller, are included in the final layout. The final layout also includes smaller test circuits such as an AND gate, a shift register and a full adder. The discussion of circuit simulation includes the calculation of SPICE model parameters based on the Rochester Institute of Technology's Microelectronic Engineering Department's NMOS process. The design and use of a standard pad frame cell based on the same fabrication process is also discussed. The final sections discuss fabrication and test of the NMOS devices and circuits using the Microelectronic Engineering Department's undergraduate student factory.

Library of Congress Subject Headings

Integrated circuits--Very large scale integration--Design and construction--Testing; Integrated circuits--Very large scale integration--Design and construction--Computer simulation

Publication Date

9-1-1990

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Fuller, Lynn

Advisor/Committee Member

Pearson, Robert

Advisor/Committee Member

Brown, George

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7874 .C5444 1990

Campus

RIT – Main Campus

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