The presence of branch instructions in an instruction stream may adversely affect the performance of a processor by introducing significant delays in the execution process. As processors become more pipelined, the impact these delays have upon performance increases. This thesis investigates why delays occur when branch instructions are encountered. It also summarizes various hardware methodologies which can alleviate the performance degradation due to these delays. Simulation results show that these hardware methodologies can improve branch performance by up to 45 percent. Some branches are inherently necessary in order to implement programming decisions. However, the use of branches within programs can inadvertently cause significant performance degradation. This thesis analyzes several methods to implement a programming decision and the performance of each method, thus providing insight into programming guidelines which can be followed to improve branch performance. Measurements of these software techniques show performance improvements of up to 178 percent.

Library of Congress Subject Headings

Reduced instruction set computers--Design and construction--Research; Computer architecture--Research; Computer engineering

Publication Date


Document Type


Department, Program, or Center

Electrical Engineering (KGCOE)


Chang, Ji-en

Advisor/Committee Member

Chang, Tony

Advisor/Committee Member

Reddy, Pratapa


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7885 .S764 1995


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