Simulation work has long been realized as a method for analyzing semiconductor processing expediently and cost-effectively. As technology advancements strive to meet increasingly stringent parameter constraints, difficult issues arise. In this paper, challenges in block mask lithography will be discussed with the aid of using simulation packages developed by Panoramic Technology®. Halo formation utilizes a 20-30° tilt-angle implantation [1]. The block mask defines the geometries of the resist opening to allow implantation of atoms to extend into the channel region. Due to designed resolution scaling and tolerance in conjunction with substrate topography, there can be undesired influence on the electrical device characteristics due to block variations. Although the block mask pattern definition is relatively simple, additional investigation is required to understand the sensitivities that drive the implant resist CD variation. In this study, block mask measurements processed using 248 nm and 193 nm illumination sources were used to calibrate the simulation work. Addition of optical proximity correction (OPC) and wafer topography geometry parameters have been shown to improve modeling capabilities. The modeling work was also able to show the benefits of a developable bottom anti-reflection coating (dBARC) process over a single layer resist (SLR) process in the resist intensity profiles as gate pitch is decreased. The goal of this work was to develop an accurate simulation model that characterizes the lithographic performance needed to support the transition into future technology nodes.

Library of Congress Subject Headings

Semiconductors--Mathematical models; Nanolithography

Publication Date


Document Type


Department, Program, or Center

Microelectronic Engineering (KGCOE)


Hirschman, Karl


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.85 .K39 2011


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