Digital copiers and printers require that processing steps be performed on image data after it is captured and before it is finally printed. Grayscale data is typically captured using an image scanner or generated using image composition software. Single bit data is usually printed using a laser, LED, ink-jet, or thermal writer. This thesis describes the design of an ASIC that implements several image processing algorithms. Image histogram modification and convolution filtering are used for operating on gray data. Ordered dither, error diffusion and thresholding convert gray data to binary. A pipe line architecture is used to maximize both the modularity and the throughput of the design. A CPU interface is used to allow flexible programming of the image processing parameters. The design is implemented and simulation stimulus is generated entirely in VHDL. A design of this type allows many of the image processing operations commonly required in digital copiers and printers to be performed in real time rather than as a pre-processing software step. The programmability of the image processing parameters makes the design suitable for a wide variety of applications. The use of VHDL for the design allows flexibility in selecting the target implementation technology for synthesis.

Library of Congress Subject Headings

Imaging systems--Design and construction--Computer simulation; VHDL (Computer hardware description language)

Publication Date


Document Type


Department, Program, or Center

Computer Engineering (KGCOE)


Brown, George

Advisor/Committee Member

Hsu, Kenneth

Advisor/Committee Member

Matteson, Ronald


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TA1632 .K445 1996


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