Wan-Fu Chen


The goal of this thesis is to design and simulate a high speed 16-bit processor chip by using RISC architecture. The high computing speed is achieved by employing a more effective four-stage pipeline. This processor executes every instruction in one clock cycle, and it won't have any delay of executing instructions when it executes Jump, Condition Jump, Call, and Return instructions. Its computing speed is 4 times faster than the speed of the Berkeley RISC II's for the 8-MHz clock. The design includes the main architectural features of the RISC: the 4-stage pipeline, the thirty-two 8-bit register bank, the 16-bit address and data paths, the internal timer, the input port, and the two output ports. The chip is designed using 2u. CMOS N well two metal layer technology. The processor runs at a clock rate of 16 MHz. The size of the chip is 10535fim by 14677um. It consists of 24,982 transistors and consumes 200mw.

Library of Congress Subject Headings

Reduced instruction set computers--Design; Computer architecture--Design; Integrated circuits--Design and construction

Publication Date


Document Type


Department, Program, or Center

Computer Engineering (KGCOE)


Hsu, Kenneth

Advisor/Committee Member

Chang, Tony

Advisor/Committee Member

Czernikowski, Roy


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.A73C43 1994


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