The purpose of this thesis is to examine asynchronous design as a possible alternative to synchronous design. Asynchronous design promises better power consumption and higher performance. In this thesis an asynchronous simulator capable of predicting asynchronous system performance is designed. The simulator is based on a probabilistic event driven model of asynchronous elements. The simulator is performance oriented only, and thus is not capable of functional simulation or verification. It provides a highly abstract view of the system. Using the simulator several design methodologies were inspected and simulated for their performance. Particular attention is paid to differences between synchronous and asynchronous methodologies. In addition several current sensor techniques were examined as a possible way of implementing asynchronous circuit completion detection. The contribution of this thesis is definition of the reasons why the current sensing is not a feasible way for completion detection, and the ability to predict the asynchronous system behavior on an architectural level.

Library of Congress Subject Headings

Asynchronous circuits

Publication Date


Document Type


Department, Program, or Center

Computer Engineering (KGCOE)


Chang, Tony

Advisor/Committee Member

Sniatala, Pawel


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7868.A79 H48 1999


RIT – Main Campus