Hash tables have been used frequently to implement organized data table storage. However, there is a great deal of overhead in executing the hash algorithm every time the table is accessed. Alternatively, a content addressable memory (CAM) is a hardware implementation of an organized data table. A CAM requires very complex hardware design for each memory cell and therefore yeilds a very low cell density on each chip. This requires a large number of expensive chips to implement a large hash table. In this thesis a simple hash function was designed into an integrated circuit using 4- micron NMOS technology. The scope of this thesis covers theoretical development, circuit design, simulation and fabrication. This chip performs a simple hashing algorithm using standard RAM to store the data and can interface to several 8-bit and 16-bit microprocessors. The design of this device is aimed at improving the speed of compilers, assemblers, and whenever fast access to organized data tables are needed.

Library of Congress Subject Headings

Hashing (Computer science); Semiconductor storage devices--Design and construction; Computer storage devices--Design and construction

Publication Date


Document Type


Department, Program, or Center

Computer Science (GCCIS)


Ellis, John

Advisor/Committee Member

Anderson, Peter

Advisor/Committee Member

Czernikowski, Roy


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.H36 K477 1987


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