The continued dominance of floating gate technology as the premier non-volatile memory (NVM) technology is expected to hit a roadblock due to issues associated with its inability to catch up with CMOS scaling. The uncertain future of floating gate memory has led to a host of unorthodox NVM technologies to surface as potential heirs. Among the mix is phase change memory (PCM), which is a non-volatile, resistance variable, memory technology wherein the state of the memory bit is defined by the resistance of the memory material. This research study examines novel, bilayer chalcogenide based materials composed of Ge-chalcogenide (GeTe or Ge2Se3) and Sn-chalcogenide (SnTe or SnSe) for phase change memory applications and explores their integration with CMOS technology. By using a layered arrangement, it is possible to induce phase change response in materials, which normally do not exhibit such behavior, and thus form new materials which may have lower threshold voltage and programming current requirements. Also, through the incorporation of a metal containing layer, the phase transition characteristics of the memory layer can be tailored in order to obtain in-situ, a material with optimized phase change properties. Using X-ray diffraction (XRD) and time resolved XRD, it has been demonstrated that stacked phase change memory films exhibit both structural and compositional dependency with annealing temperature. The outcome of the structural transformation of the bottom layer, is an annealing temperature dependent residual stress. By the incorporation of a Sn layer, the phase transition characteristics of Ge-chalcogenide thin films can be tuned. Clear evidence of thermally induced Ge, Sn and chalcogen inter-diffusion, has been discerned via transmission electron microscopy and parallel electron energy loss spectroscopy. The presence of Al2O3 as capping layer has been found to mitigate volatilization and metallic Sn phase separation at high temperatures. Two terminal PCM cells employing these bilayers have been designed, fabricated and tested. All devices exhibit threshold switching and memory switching behavior. By the application of suitable voltage programming pulses, RESET state switching can be accomplished in these devices, thus demonstrating single bit memory functionality. A process for integrating bilayer PCM technology with 2 µm CMOS has been designed and developed. The baseline RIT CMOS process has been modified to incorporate 12 levels of photolithography, 3 levels of metal and the addition of PCM as a BEOL process. On electrical testing, NMOS connected PCM devices exhibit switching behavior. The effect of the state (SET/RESET) of the series connected PCM cell on the drain current of the NMOS has also been investigated. It is determined that threshold switching of the PCM cell is essential in order to observe any change in MOS drain current with variation in drain voltage. Thus, successful integration of bilayer PCM with CMOS has been demonstrated.

Library of Congress Subject Headings

Semiconductor storage devices--Materials; Metal oxide semiconductors, Complementary--Design and construction; Chalcogenides; Phase transformations (Statistical physics)

Publication Date


Document Type


Student Type


Degree Name

Microsystems Engineering (Ph.D.)

Department, Program, or Center

Microsystems Engineering (KGCOE)


Kurinec, Santosh


Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7895.M4 D48 2011


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