Clock Tree Synthesis (CTS) is a complex and in depth process that, in modern designs, would take an individual months if not years to get a working design. Tools such as Cadence Innovus and Synopsys ICC provide excellent support for CTS and can be used to create well optimized trees; allowing the user to edit the tree’s generation down to a single buffer. However, even these tools can fall short of a perfectly optimized route and oftentimes need a capable user to direct them in the right direction just to get a functioning clock tree. The aim of this work is to provide an additional tool to further aid users in pursuit of fully functional and highly optimized clock trees. The developed network is an evolutionary neural network, built on NEAT-Python, trained on ten variations of a results character conversion block designed for a dual-tone multi-frequency receiver. The network is meant to provide users with clock tree generation parameters such that the routed tree will be optimal. The network’s success is evaluated based on its growth throughout training and its ability to suggest optimal parameters for one hundred variations of the same design. It is found that the network grows steadily, suggesting that given enough time it could master CTS. That being said, the final test reveals that the network is only slightly superior to default CTS parameters and is far too inconsistent to be considered successful. These results are carefully evaluated to suggest improvements for future attempts to develop a similar neural network.

Publication Date


Document Type

Master's Project

Student Type


Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical and Microelectronic Engineering, Department of


Kate Gleason College of Engineering


Mark A. Indovina

Advisor/Committee Member

Ferat Sahin


RIT – Main Campus