The surge in demand for semiconductors and AI-driven applications has led to an amplified requirement for swift and efficient semiconductor design production cycles. These shortened cycles, however, pose a challenge as they reduce the time available for complex chip design and verification, consequently increasing the likelihood of producing error-prone chips. Current research concentrates on utilizing a Lookup Table (LUT) based pPIM (Programmable Processor in Memory) technology to deliver efficient, low-latency, and low-power computation specifically tailored to 4-bit data requirements, ideal for repetitive and data-expensive AI algorithms. This thesis presents the user-defined Generation 2 pPIM, a redesigned and enhanced version of the existing static Generation 1 architecture, offering a scalable, configurable, and fully automated framework to expedite the design, verification, and implementation process. The user-defined Gen 2 pPIM Cluster, consisting of nine interconnected user-defined Gen 2 pPIM Cores and an included Accumulator, extends the capability to execute complex operations like Multiply-and-Accumulate (MAC). Both the Gen 2 pPIM Core and Gen 2 pPIM Cluster undergo extensive verification and testing. A Python-based suite has been developed to enable user-specific Gen 2 pPIM Core and Gen 2 pPIM Cluster design and verification efficiently, providing an end-to-end automated toolkit catering to the user’s specific needs. All variants of core and cluster design are benchmarked with 28nm, 65nm and 180nm technology libraries and are compared for area, power and timing.

Library of Congress Subject Headings

Computer hardware description languages; Semiconductors--Design; Computer architecture; Memory management (Computer science); High performance processors

Publication Date


Document Type


Student Type


Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Department of Electrical and Microelectronic Engineering (KGCOE)


Mark A. Indovina

Advisor/Committee Member

Amlan Ganguly

Advisor/Committee Member

Dorin Patru


RIT – Main Campus

Plan Codes