While both processing and memory architectures are rapidly improving in performance, memory architecture is lagging behind. As performance of processing architecture continues to eclipse that of memory, the memory architecture continues to become an increasingly unavoidable bottleneck in computer architecture. There are two drawbacks that are commonly associated with memory accesses: i) large delays causing the processor to remain idle waiting on data to become available and ii) the power consumption required to transfer the data. These performance issues are especially notable in research and enterprise computing applications such as deep learning models. Even when data for an application such as this is transferred to a cache before processing to avoid the delay, the large power cost of the transfer is still incurred. Processing-in-memory (PIM) architectures offer a solution to the issues in modern memory architecture. The inclusion of processing elements within the memory architecture reduces data transfers between the host processor and memory, thus reducing penalties incurred by memory accesses. The programmable-PIM (pPIM) architecture is a novel PIM architecture that delivers the performance enhancements of PIM while delivering a high degree of reprogrammability through the use of look-up tables (LUTs). A novel instruction set architecture (ISA) for the pPIM architecture facilitates the architecture's reprogrammability without large impacts on performance. The ISA takes a microcoded approach to handling the control signals of the pPIM control signals. This approach allows variable-stage instructions at a low additional cost to the overall power and area of the architecture. The versatility of the pPIM architecture enables MAC operations and several common activation functions to be modeled for execution on the architecture. As a measure of performance, post-synthesis models of both the pPIM architecture and the ISA are generated for CNN inference. As a proof-of-concept an FPGA model of the pPIM architecture is developed for representations of a single layer neural network (NN) model for classification of MNIST images.

Library of Congress Subject Headings

Computer architecture--Design; Memory management (Computer science); High performance processors; Neural networks (Computer science)

Publication Date


Document Type


Student Type


Degree Name

Computer Engineering (MS)

Department, Program, or Center

Computer Engineering (KGCOE)


Amlan Ganguly

Advisor/Committee Member

Mark Indovina

Advisor/Committee Member

Cory Merkel


RIT – Main Campus

Plan Codes