This paper presents the design of a 32-bit RISC processor, which is then mapped to the backend of GCC so basic C code can be compiled successfully to the processor. There are many design decisions that go into the construction of a processor. The instruction set architecture gives away a lot of information regarding the individual instructions that the processor will have, the memory architecture, as well as how I/O peripherals will be handled. Additionally, the hardware implementation of the processor needs to be kept in mind when crating the design. Pipelining can often help with processor speed, while cache implementation can assist in memory speed. After designing the processor, GCC’s backend needs to be analyzed to port it to function with the processors individual opcodes. Once GCC can compile its C code to an assembly language which is able to assemble into machine code that matches up with the opcodes the processor was created for, the machine code can be written into the processor’s program memory and executed successfully. This paper also talks about different design decisions that are made during the process of creating a processor, as well as the general makeup of the GCC compilation process.

Publication Date


Document Type

Master's Project

Student Type


Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)


Mark A. Indovina

Advisor/Committee Member

Sohail A. Dianat


RIT – Main Campus