A model is created for the number of integrated circuits that are good from each wafer on which they are fabricated. The goal is to separate the random or common cause loss from the systematic or special loss. The random loss from this type of process is modeled so that false alarms indicating systematic loss are less likely to occur and so that the structure of the systematic loss can be determined.
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Department, Program, or Center
School of Mathematical Sciences (COS)
Farnsworth, David L. and Long, Michael E., "Modeling the Random Component of Manufacturing Yield of Integrated Circuits." (2010). International Journal of Engineering and Technology, 2 (6), 402-405. Accessed from
RIT – Main Campus