Abstract

Functional verification often takes more effort than designing the system itself, especially when the design departs from the synchronous, globally clocked style that verification tools assume. Asynchronous or clockless circuits are an example of this. They use local request and acknowledge handshaking instead of a global clock, which reduces dynamic power and eliminates clock-distribution and skew problems. However, this also means that standard verification methods that rely on a single periodic clock no longer apply. This thesis introduces a constrained-random, coverage-driven verification environment for a four-stage asynchronous RISC-V processor. The environment is built in SystemVerilog using the Universal Verification Methodology (UVM) and is anchored to the four-phase bundled-data handshake that moves data between the processor’s pipeline stages. A C++ reference model connected through the Direct Programming Interface is the golden model. A self-checking scoreboard compares the architectural state against it at every retirement. The system is tested with both random and directed instruction streams at the register-transfer and gate levels. Coverage is measured by eleven covergroups and by ten assertion modules that contain 174 assertions. The environment reaches 94.40 percent overall coverage, with 92.76 percent code coverage and every assertion exercised (Table 6.1, 100,000 instructions). Checking against the reference model and the assertion suite exposed ten functional defects in a design that had previously been checked only by directed simulation. Nine of these were faults in the register-transfer source and were corrected. The tenth is an immediate load-use dependency, which is a limitation of the hardware rather than a coding error, and the testbench works around it.

Publication Date

8-2026

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering

College

Kate Gleason College of Engineering

Advisor

Mark A. Indovina

Advisor/Committee Member

Dorin Patru

Advisor/Committee Member

Carlos Barrios

Campus

RIT – Main Campus

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