Clayton Koppi

Abstract

Integrated circuits grow more complex as digital designers implement more features on a project. All modern integrated circuits require some form of testing in order to prove that their functionality matches the design requirements. As the complexity of a design increases, the number of potential bugs increases dramatically. The need for a testbench that is reusable, modular, and organized is apparent for modern integrated circuits. Verification is the process of proving the design matches its requirements, and discovering bugs in simulation. The business motivation behind verification is ensuring the product will work before starting the costly and long fabrication process. This project attempts to verify a DTMF Receiver module, and measure its behavior beyond the requirements. A proper testbench was constructed to evaluate the detection of digits in response to μ-Law compressed PCM digital signals. The testbench was written in the SystemVerilog verification language, and followed the Universal Verification Methodology (UVM). UVM provides a class library to organize a testbench into modular classes that are reusable, easy to maintain, and takes advantage of object-oriented programming language tools. This paper describes the verification of a DTMF Receiver in accordance with its requirements. The second part of the paper explores how much the input data can vary from ideal and still detect digits. The efforts of the verification plan, architecture, and results are presented in this paper.

Publication Date

5-2024

Document Type

Master's Project

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical and Microelectronic Engineering, Department of

College

Kate Gleason College of Engineering

Advisor

Mark A. Indovina

Advisor/Committee Member

Ferat Sahin

Campus

RIT – Main Campus

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