This work is a wide-reaching study of the factors that impact the in-situ crystallization of thin films of amorphous silicon into low-temperature polycrystalline silicon (LTPS) by flash lamp annealing (FLA) on glass substrates, which is used to develop thin film transistors (TFTs) with an eye towards display applications. The body of research surrounding FLA LTPS is thus advanced by identifying several challenges towards industrial integration and exploring solutions involving device configuration, novel methods of dopant introduction and activation, and novel TFT material systems. It is unlikely that FLA will ever produce LTPS superior to the laser-annealing techniques currently dominating the market, but its significant improvements in throughput and roll-to-roll compatibility make it an attractive complementary technology. In this work, existing FLA LTPS TFT research is expanded into complementary metal-oxide-semiconductor (CMOS) logic to take advantage of the n- and p- channel compatibility of LTPS over competing amorphous oxide technology. A processing alternative is developed for scaling these devices down to current dimensions of liquid crystal display (LCD) transistor backplanes and then further improved by exploring a silicon ion self-implant to preamorphize the polycrystalline lattice structure, allowing enhanced dopant activation at temperatures compatible with thermally-fragile substrates. This method is also shown to be compatible with a self-aligned device configuration for ease of processing and reduced parasitic capacitance. Additionally, a new strategy for producing bottom-gate LTPS devices (a consistent challenge for laser-annealed LTPS) is presented by incorporating a transparent conductive oxide as a gate structure. The increased thermal mass provided by the bottom gate is harnessed to improve the impact of channel crystallization at lower pulse intensity, producing devices with extremely high channel mobility at low drain voltage. Monolayer Doping (MLD) is demonstrated to be compatible with FLA LTPS, utilizing a simultaneous anneal to both crystallize amorphous silicon and activate selectively self-assembled MLD-adhered dopants. MLD phosphorus n-channel TFTs are presented with activation on par with that of ultra-shallow MLD junctions on bulk silicon. Further, Gallium MLD is demonstrated for the first time, successfully producing p-channel TFTs with FLA. The material system of FLA-crystallized silicon on chromium, already well established in the micrometer-thick film range for PV applications, is given an in-depth investigation in the nanometer thin film range for TFT applications. A unique set of crystallization patterns and texture on the nanometer scale is revealed and characterized to determine the extent, cause, and impact of chromium redistribution in this material, which is also explored as a predictable and edge-directed morphology of FLA LTPS for a wide variety of device configurations. Finally, the individual advancements in this work are explored in many combinations in a wide multi-process study to determine their efficacy as techniques for producing FLA LTPS TFTs. Using this broad information, the field of flash-lamp crystallized TFTs is advanced and several challenges are more specifically identified as a foundation for future research.

Library of Congress Subject Headings

Thin film transistors--Materials; Silicon crystals--Electric properties; Annealing of crystals

Publication Date


Document Type


Student Type


Degree Name

Microsystems Engineering (Ph.D.)

Department, Program, or Center

Microsystems Engineering (KGCOE)


Karl D. Hirschman

Advisor/Committee Member

Parsian Mohseni

Advisor/Committee Member

Santosh Kurinec


RIT – Main Campus

Plan Codes