A hierarchical analysis of variance was executed on both critical dimension and film thickness data to prove manufacturability of a double layer resist process as compared to an existing device process. Testing was designed to provide estimates of variance on a die—to—die, wafer—to— wafer, and run-to—run basis. Ion implant mask sidewall angle and process repeatability were other concerns investigated. The double resist process displayed improvement in all phases of the process examined except the run—to— run variance of the polysilicon film thickness. More testing is required to determine if the possible cause was related to the process or some outside factor.
Jech, Joseph Jr
"Evaluation of a Double Resist Process,"
Journal of the Microelectronic Engineering Conference: Vol. 5:
1, Article 10.
Available at: https://repository.rit.edu/ritamec/vol5/iss1/10