The effects of an n-type and p-type doped polysilicon gate fabricated over both an n-type and p-type substrate for MOS capacitors with different polysilicon doping processing schemes was evaluated and compared to the current RIT process that utilizes a metal gate. Both boron and phosphorous Spin on dopants were used to supply the conduction for the gate region of the polysilicon capacitors. Bias temperature bias was performed to evaluate the mobile ion contamination non-ideality, while a FORTRAN program was written to extract important capacitance voltage parameters from the actual C-V plots obtained that are of interest for MOS technologies
"Capacitance-Voltage Characterization for Polysilicon Gate MOS Capacitors,"
Journal of the Microelectronic Engineering Conference: Vol. 4:
1, Article 22.
Available at: https://repository.rit.edu/ritamec/vol4/iss1/22