This project developed a test chip designed to standardize the testing requirements and characterize bipolar, PMOS and CMOS processes at Rochester Institute of Technology. The comon process monitors were designed to test resistivity, opens and shorts, contact resistance and capacitance. The photolithograPhic monitors were designed to test image resolution and alignment. Process specific discrete devices were designed to test parainetrics and leakage currents. The test chip dies were primarily designed to be inserted onto the mask to eliminate the the need for process monitors on each die and secondly, to periodically monitor the performance of a student run integrated circuit factory.
Klem, Craig R.
"Design of Test Die For Monitoring Manufacturing at RIT,"
Journal of the Microelectronic Engineering Conference: Vol. 2:
1, Article 20.
Available at: https://repository.rit.edu/ritamec/vol2/iss1/20