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SOI (Silicon on Insulator) technology is an option in improving device performance as smaller devices run into scaling challenges. The devices for this study were fabricated using a FIPOS (Fully Isolated Porous Oxidized Silicon) process, which results in localized SOJ active regions. The oxidation of electrochemically etched porous silicon (PSi) has demonstrated success in the formation of device quality localized SOl for CMOS applications [1,2]. The formation of PSi can be done selectively by controlling the Fermi level in areas to be etched or not etched, which is typically (lone by adjusting the level of (loping [1]. An alternative method is to introduce a reversible donor species such as protons [2] or fluorine (this work) for the selective formation of islands of crystalline silicon surrounded by porous silicon. Implanted fluorine in silicon has demonstrated a donor effect upon annealing at low temperature (600°C), which is reversible as the fluorine outdiffuses (luring higher temperature annealing (1000°C). This technique has been used to form ~ crystalline silicon active regions with thickness less than 200 nm completely surrounded by oxidized porous silicon [3], shown in figure 2. This study involves the fabrication and characterization of nFETs on the active areas to investigate the electronic integrity of the silicon device regions.

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